In modern semiconductor processing technology, when an interconnection device having a high average aspect ratio is needed within a relatively thick insulating film, three discrete processing sequences are commonly used to is form three separate insulating films and separate interconnection devices within each insulating film. The individually formed interconnection devices are stacked on top of one another in order to contact each another. The repeating sequence of processing steps used to form such a structure using conventional processes is illustrated in FIG. 1A through FIG. 1F.
When forming an interconnect device in a relatively thick insulating film such as a dielectric film, individual layers (each containing dielectric material and a portion of the interconnection device) must be formed separately. For each layer, a dielectric film is deposited. The dielectric film is patterned to form an opening; the patterning material such as photoresist is removed; a barrier film is deposited within the opening and on top of the dielectric film; a bulk conductive film is deposited over the barrier layer; then, the structure is polished to remove the overburden of the interconnect materials from the upper surface of the dielectric layer. Next, another layer of dielectric material is formed and the process is repeated. Later, a third layer of dielectric material is formed and the process is again repeated.
Now turning to FIG. 1A, a contact film 3 is formed over substrate 1. The first dielectric film 5 is formed over contact layer 3. The first dielectric film 5 is patterned then etched to provide an opening 2 within the first dielectric film 5. A barrier film 12 is formed over the structure, and then conductive film 11 is formed over the barrier film 12. Portions of films 11 and 12 which lie above upper surface 8 of first dielectric film 5 are then planarized by polishing.
Now turning to FIG. 1B, the structure is shown after the connection device is formed within first dielectric film 5. Polishing processes are used to form a substantially smooth top surface 8'. Top surface 8' forms the upper surface of a section which will be the bottom section of the completed interconnection device.
FIG. 1C shows the structure after a second dielectric film 7 has been formed over the first dielectric film 5. After an opening 4 is formed within the second dielectric film 7, a barrier film 14 and a conductive film 13 are sequentially deposited in a manner similar to barrier film 12 and conductive film 11 as in FIG. 1A. The process sequence is continued with polishing and the result can be seen in FIG. 1D.
Now turning to FIG. 1E, a third dielectric film 9 is formed. Third dielectric film 9 is patterned to form opening 6. Opening 6 is filled with barrier film 16 and conductive film 15, deposited in sequence, after the patterning material has been removed.
Now turning to FIG. 1F, the final structure formed using conventional processes is shown having an upper surface 17. The layered dielectric film consists of three distinctly deposited dielectric films 5, 7, and 9, formed over contact film 3. The barrier layers 12, 14, and 16 are all separately formed. Conductive films 11, 13, and 15 are also all individually formed. Each dielectric film 5, 7, and 9 must be separately patterned to form corresponding openings 2, 4, and 6 into which corresponding portions of the interconnect device will be formed. The patterning material such as photoresist must be removed each time. Each dielectric film 5, 7, and 9 must be individually polished. The device formed using conventional processes requires several steps as well as extra materials. For example, the conductive and barrier films are each deposited three times, and the overburden of these materials is also removed three times, adding material expenses.
Barrier films 12, 14, and 16 include horizontal components which isolate portions of the conductive films 11, 13, and 15 from each other. This horizontal interface between conductive portions of the film causes current crowding which is undesirable. When current is passed through an interconnection device, it is generally desirable to spread the current across the area of the device, so as to minimize current crowding effects such as electromigration failures. The horizontal interface also increases contact resistance because the barrier materials have a much higher resistivity than the bulk conductive films.
Even with the above shortcomings such as additional processing steps and the resulting horizontal interfaces of barrier materials, the use of individually formed sections of an integrated interconnection device may be required when an opening with a high aspect ratio must be filled, because of the limitations of conventional processing technology. The aspect ratio of a device is defined as the height divided by the width. A very narrow interconnection device formed within a relatively deep dielectric film has a high aspect ratio.
When such a structure is required, the limitations of conventional processing technology require that these openings be individually formed within films which are individually deposited to form discrete layers. These discrete layers are stacked to combine to form an overall high-aspect ratio interconnection device. These process steps are necessary because of the difficulty of forming a very deep opening within a dielectric film, and subsequently filling the opening completely with interconnection materials, using conventional processing technology.